AIWA CSDTD21EZ/U
Instrukcja Serwisowa

Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Pin Name LVSS RVSS RCHO RVDD MUTER XVDD XOUT XIN XVSS SBSY EFLG PW SFSY SBCK FSX WRQ RWC SQOUT COIN CQCK RES T11 16M 4.2M T5 CS T1

I/O � O O O

Description Left channel one-bit D/A converter ground. Must be connected to 0V. Right channel one-bit D/A converter ground. (Must be connected to 0V.) Right channel onr-bit D/A converter output. Right channel one-bit D/A converter power supply. Right channel one-bit D/A converter mute output. (Not used) Crystal oscillator power supply. Connections for a 16.9344 MHz crystal oscillator element.

I O O O O in standby state. (Not used) I O O I O I I readout clock input pin. This is Schmitt input. I O O O I I (Must be connected to 0V if not controlled.) I Test input. No pull-down resistor. (Must be connected to 0V.) Reset input. This pin must be set low briefly after power is first applied. Test output. Leave open. (Normally output a low level). (Not used) 16.9344 MHz output. (Not used) 4.2336 MHz output. Test input. A pull-down resistor is built-in. (Must be connected to 0V.) Chip seledt input. A pull-down resistor is built-in. Subcode readout clock input. This is a Schmitt input. Output pin for the 7.35 kHZ synchronization signal divided from the crystal oscillator. (Not used) Subcode Q output standby output. Read/write control input. This is a Schmitt input. Subcode Q output. Command input pin from control microprocessor. Input for both the command input acquisition clock and the SQOUT pin subcode Crystal oscillator ground. (Must be connected to 0V.) Subcode clock synchronization signal output. (Not used) C1, C2, sigle an double error correction monitor. (Not used) Subcode P, Q, R, S, T, U and W output. (Not used) Subcode frame synchronization signal output. This signal falls when the subcode are

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