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3. Operation
A. Communication circuit
This circuit is used to communicate with the copier body.
+5V +5V R6 470 CN1,4 TXD 4 R8 R7 4.7K R64 100 3 Test pat29 C16 100PF CN1,2 DSR 2 HD74HC14FP 4
IC6.2 IC2.2
R59 4.7K 4 HD74HC14FP IC6.1 2 1 VCC-+5V GND-SGND Test pat24 6 IC6.3 5 Test pat26 80
Test pat25
IC11
79
Test pat23 C20 100PF
3
CN1,3
RXD
IC2.3 5 6
HD74LS06FP
HD74LS06FP
Test pat27 4
1 CN1,1 DTR
R63 100
3 HD74LS06FP +5V R74 10K
Test pat28
3
5 CN1,5 CN1,6 CN1,7
CN1,8
R62 100
Test pat30 C2 0.10µF
IC2.1
1
2
Test pat31 11
IC6.5 10
Test pat35
RESET SGND JINT
N.C
Main body reset
6 7 8 SGND SGND HD74HC14FP HD74LS06FP
The input and the output of each signal are as follows:
[a] DTR CN1-1 pin
The input from the main body. When LOW (0V) at IC11-4 pin, it means the main body has the control to transmit.
[b] DSR CN1-2 pin
The output in the sorter side. When HIGH (+5V) at IC11-3 pin, IC11-4 pin turns from LOW (0V) to HIGH (+5V) then to LOW again. During that period, the sorter has the control to transmit.
[c] TXD CN1-4 pin
The input from the main body. When IC11-79 pin turns from HIGH (+5V) to LOW, data reception is started.
[d] RXD CN1-3 pin
The output in the sorter side. When IC11-80 pin turns from HIGH (+5V) to LOW, data transmission is started.
[e] RESET CN1-5 pin
The reset signal from the main body. When CN1-5 pin is HIGH (+5V), the CPU (IC11) is reset.
B. Reset circuit
This circuit is the reset circuit.
+5V 2 5 VCC C23 0.10µF 4 RES
D1 DSA010 A K 3 CK 8 1 6
6
+5V
R72 10K IC6.4 19
Test pat33
+5V R75 10K 8 2
Test pat64 3
IC11
IC5 MB3773FP *RES GND CT VREF VS 7 C22 470PF
IC7.1Y
1
7
HD74LS06FP + HD74HC02FP VCC-+5V GND-SGND
C17 1µF
SGND
Main body reset
This circuit is used to generate the CPU reset signal, and is composed of IC5 and its peripheral circuits.
