SONY TAE9000ES
Instrukcja Serwisowa

Pin No. 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Pin Name TSTD VSS8 VDD5 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 VSS9 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31 XOE VSS10 VDD6 CAS XWE RAS EA0 EA1 EA2 EA3 EA4 VSS11 VDD7 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 VSS0 EA13 EA14 EA15 EA16 TSTA PLDIVF PLDIVB CLKI CLKO

I/O I � � I/O I/O I/O I/O I/O I/O I/O I/O � I/O I/O I/O I/O I/O I/O I/O I/O O � � O O O I/O I/O I/O I/O I/O � � I/O I/O I/O I/O I/O I/O I/O O � O O O O I I I I O

Function Test data input �L� = normal �H� = test Ground Power supply (+3.3V) External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output Ground External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM data input/output External RAM output enable Ground Power supply (+3.3V) External RAM column address strobe External RAM write enable External RAM raw adress storobe External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input Ground Power supply (+3.3V) External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input External RAM address output/test data input External RAM address output Ground External RAM address output External RAM address output External RAM address output External RAM address output Test data input �L� = normal �H� = test PLL input frequency setup PLL output frequency setup Master clock input Master clock output �L� = 256Fs �H� = 128Fs �L� = 768Fs �H� = 1024Fs

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