Schematy są ale można wysilić się i zrobić kolorowy skan i o większej rozdzielczości. Wtedy schematy płytek będą czytelniejsze. Całość super jako wartość merytoryczna. Wszystkie dane potrzebne do podłączenia różnego rodzajów urządzeń takich gramofon, CD itd.
jedyne do czego mogę mieć zastrzeżenie to jakość zdjęć zawartych w przesłanej instrukcji serwisowej ponieważ są fatalnej jakości, praktycznie nieczytelne. tak poza tym jestem zadowolony to jest to czego szukałem.
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Step 7: 1st DSP
A
k
CN351 (Pin 20) RESET
r
CN351 (Pin 16)
For the following diagnosis, a digital oscilloscope must be used. SPICLK
Is the logic of RST_1 "H" ?
No
Check the output from the DIGITAL MOTHER Assy.
Is the clock signal output while the voltage at SPIDS_1 is "L"?
No
Check the output from the DIGITAL MOTHER Assy.
m
Yes R122
s
Yes R124
B
Is the logic of RST_1 "H" ? Yes Is the logic of RST_1 maintained
No
Check the parts and patterns in the path.
Is the clock signal output while the voltage at SPIDS_1 is "L"?
No
Check the parts and patterns in the path.
at "H"? (Does it fall to become "L" periodically?)
No
It is likely a boot error. (It is very difficult to diagnose which peripheral part of the DSP is in failure.)
t
Yes CN351 (Pin 19) MOSI
n
C
Yes R102 REQ_1
Is the clock signal output while the voltage at SPIDS_1 is "L"?
No
Check the output from the DIGITAL MOTHER Assy.
Does the logic become "H" for a moment when the input stream is changed?
u
No The 1st DSP is in failure. Replace it.
Yes R126
o
Yes CN351 (Pin 21)
Is the clock signal output while the voltage at SPIDS_1 is "L"?
No
Check the parts and patterns in the path.
D
Does the logic become "H" for a moment when the input stream is changed?
v
No Check the parts and patterns in the path.
Yes R125 MISO
p
Yes CN351 (Pin 17) SPIDS_1
Is the clock signal output while the voltage at SPIDS_1 is "L"?
No The 1st DSP is in failure. Replace it.
Does the logic become "L" for a moment when the input stream is changed?
w
No Check the output from the DIGITAL MOTHER Assy.
Yes
CN351 (Pin 18)
q
E
Yes R123
Is the clock signal output while the voltage at SPIDS_1 is "L"? Yes No Check the parts and patterns in the path.
No
Check the parts and patterns in the path.
Does the logic become "L" for a moment when the input stream is changed?
It is very difficult to diagnose which part is in failure.
