AIWA XDDV480
Instrukcja Serwisowa

IC DESCRIPTION - 3/9 (M12L16161A-7T)-2/2
Pin No. Pin Name I/O Description This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising 34 CKE I edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for powerdown and clock suspend modes. 35 CLK I CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. DQM controls input/output buffers. - Read operation: If DQM is High, The output buffer becomes High-Z. If the DQM is Low, the 36 UDQM I output buffer becomes Low-Z. - Write operation: If DQM is High, the previous data is held (the new data is not written). If DQM is Low, the data is written. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC VCCQ MD8 MD9 VSSQ MD10 MD11 VCCQ MD12 MD13 VSSQ MD14 MD15 GND � � I/O � I/O � I/O � � I/O Not used 3.3 V is applied. (VCCQ is for the output buffer.) Data is input and ouput from these pins. These pins are the same as those of a conventional DRAM. Ground is connected. (VSSQ is for the output buffer.) Data is input and ouput from these pins. These pins are the same as those of a conventional DRAM. 3.3 V is applied. (VCCQ is for the output buffer.) Data is input and ouput from these pins. These pins are the same as those of a conventional DRAM. Ground is connected. (VSSQ is for the output buffer.) Data is input and ouput from these pins. These pins are the same as those of a conventional DRAM. Ground is connected. (VSS is for the internal circuit.)

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