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Dla tego produktu nie napisano jeszcze recenzji!
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Schematy są ale można wysilić się i zrobić kolorowy skan i o większej rozdzielczości. Wtedy schematy płytek będą czytelniejsze. Całość super jako wartość merytoryczna. Wszystkie dane potrzebne do podłączenia różnego rodzajów urządzeń takich gramofon, CD itd.
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Szybko, sprawnie i tanio. Serwis godny polecenia. Będę polecał innym
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Ogólnie jest OK, z wyjątkiem obrazu płyty głównej, który jest miejscami mało czytelny, ale można sobie poradzić.
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Dokładna dokumentacja, pomogła w szybkiej naprawie telewizora. Dziękuję!
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jedyne do czego mogę mieć zastrzeżenie to jakość zdjęć zawartych w przesłanej instrukcji serwisowej ponieważ są fatalnej jakości, praktycznie nieczytelne. tak poza tym jestem zadowolony to jest to czego szukałem.
EN 98
9.3.1
9.
FTP1.1E
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Events in SEMI-STANDBY 1. The set can be in semi-standby during Time extraction, EPG loading, or P50 (Easylink) recording. The semistandby state is ended when: � Time extraction has finished. � P50 recording has finished. � EPG loading has finished. � A P50 recording starts during EPG loading. � A user event "On" or "Standby". � The set goes into protection. 2. If the standby bit is not set (after user event), the PDP is switched "on". 3. If a P50 recording or an EPG loading has to start, the set stays in semi-standby. If the P50 recording has to start during EPG loading, the P50 has priority. 4. If there is no P50 recording or EPG loading, the set goes to standby. Events from ON to SEMI-STANDBY/STANDBY 1. The set can be switched to standby: � Via the RC (to semi-standby). � Via the MENU button on the top control, long press (to semi stand by). � Via a protection (to standby). 2. The running instructions are finished. 3. The PDP is switched "off"; this is controlled by the OTC by means of the STANDBY line. � Sound is muted � If there was a protection, the STANDBY line is put "high", and the set goes to standby. If there was no protection, the set goes to semi-standby. After an event in semi-standby, the set goes to standby. Protections are disabled. The OTC sets the STANDBY line "high", this switches "off" the main power supply, and only the standby supply remains working. 8. The set is in standby. 4. 5. 6. 7.
Power Balance Table 9-1 Total power balance overview Voltage +3V3-DISP +5V-DISP +5V2-DISP +8V-DISP +9V-STBY +9V-STBY-SW Value Current P_max Remarks (max) 3.3 V 5V 5.2 V 8.6 V 9V 9V 3.6 0.8 0.3 0.4 12 4 1.6 3.4 Standby voltage
9.3.2
Switch On/Off Via the ON/OFF knob on the side the set can be switched �on� or �off�, although when �off� not all power is removed. Only by disconnecting the mains power cord from the power socket all power is really gone.
9.3.3
Power States There are four different power states. Some characteristics of these are summarised in the "Power states" table. Table 9-2 Power states overview On/Off switch
X OFF
Power state
OUT (mainscord disconnected) OFF
Remarks
No power Only standby supply is working OTC not powered Main supply not working No LED is "on" Standby supply is working Red LED is "on" (in Europe and in US) Standby supply is working Main supply is working PDP is not active EPG loading and P50 recording possible (Europe) Time extraction (Europe and US) Red and Green LEDs are "on" The set is working Green LED is "on" (in Europe and in US)
STAND BY (1) SEMI STAND BY
ON ON
9.4
9.4.1
Input/Output (I/O)
Introduction The chassis follows the standard SCART specification: � The presence of the incoming source is detected via pin 8 of the SCART signal. � The Aspect Ratio of the incoming source is derived from the voltage level on SCART pin 8. The pin 8 information is handled by the HIP for SCART 1 and 2 and by the OTC for SCART 3. � � The P50 in/out is handled via P1-4 and P3-7 of the OTC. RGB sources break in with an additional fast blanking signal that is detected by the HIP. The HIP then internally chooses other signal processing. RGB sources that only have fast blanking and no pin 8 status do not overrule the main TV source. There is no automatic break in detection � � for the front input. The HIP for further image processing does the detection between Y/C and CVBS automatically. When Y/C is detected, the HIP will add Y and C signal to compose CVBS again. This addition should be overruled by software at the moment any Y/C signal is the source and the presence of a P50 Y/C video recorder is detected: only Y signal is directed to record out (C is already hardwired to EXT 2 out). Note: P50: Chroma-out is pin 7, Chroma-in is pin 15. NonP50: both Chroma-out and -in is pin 15 (hardwiring C to pin � 7 out; non-P50 not supported). The signal on MONITOR_OUT follows the incoming source, except in case the incoming source is EXT2, YPbPr-2fH, or VGA. Then the output signal should be FRONTEND_OUT.
ON
ON
Events from OFF to SEMI-STANDBY or ON (See also figure "Step wise start-up diagram" in chapter "Service Modes, Error Codes, and Fault Finding"). 1. The set is in "off" state until the ON/OFF switch is switched to "on". The standby voltage +5V-DISP becomes available, the OTC resets, the I/O pins are initialised, and the watchdog is enabled. The set comes in standby mode. � The sets leaves the stand by mode if: � A time extraction must be started (after every start up). � A P50 recording has to start. � An EPG loading has to start. � The Standby bit is set to "off"; when a user switches on the set, the standby bit is also set to "off". 2. The STANDBY line is set to "low", the +5V_SW is "on", the relay closes, and the LCD AUX supply starts up (8V6 is present). 3. The rest of the ICs are initialised. The EBILD is initialised min 400 ms after the standby line is set to "low". 4. If the standby bit was set, the set goes into semi-standby until: � The time extraction is done. � The P50 recording has finished. � The EPG loading has finished. 5. If the standby bit was not set, the PDP is switched "on". The PWR-OK-PDP signal from the supply is received at the EBILD to inform the main processor of proper operating PDP supply.
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