SONY BVM-D14H5U
Instrukcja Serwisowa

5. OSD Insertion Circuit The on-screen display of the R-signal is realized by inserting the OSD blanking with IC1300 (2/3) and by inserting the OSD with IC1304 (1/3). The WINDOW signal that is used during the AUTO W/B adjustment is created by the character generator, and uses the same signal line in the same way for character display. The same insertion operation is performed in the G and B signals in the same way. 6. CUT-OFF Circuit CUT-OFF of the R-signal is performed by IC1304 (2/3, 3/ 3). The same cut-off operation is performed in the G and B signals in the same way. 7. CXA1739 Peripheral Circuit The RGB signal is input during the normal operation and the color difference signal is input during the blue-only mode. (The B-signal is input to the Y input connector.) CXA1739 has the built-in auto cut-off loop. The auto cutoff reference pulse is inserted into every H. period in the order of R, G then B channels at the end of the V. BLKG period (during the 3H period immediately after the rise-up of the V. pulse that is supplied to pin-18) in the output signal from CXA1739. The return pulse of the reference pulse is buffered by Q1402 and input to IC1401 pin-25. The return pulse that is input to pin-25 is compared with the BIAS control voltage by the voltage comparator. The error signal from the comparator is used to shift the DC output voltage until the return pulse agrees with the adjustment voltage. This circuit operation is performed to prevent the changing of the cut-off level caused by the drift of CRT or of the drive circuit. Q1431 to Q1434 in the R-signal output circuit remove the smear that occurs inside the IC. The same circuit operation is performed in the G-channel and the B-channel too. 8. ABL Circuit The ABL circuit consists of Q1460 for ABL and Q1461 for BRT ABL. The ABL voltage from the deflection block is input the respective emitters of Q1460 and Q1461. The voltagedivided DC voltage of the ABL signal is input the respective bases of Q1460 and Q1461. Their collectors are connected to IC1401 pin-46 (PIC CONT) and pin-7 (BRT CONT) respectively. When these transistors are turned on, the ABL operation can be performed by decreasing their respective control voltages.
BVM-D14H1U/D14H5U/D14H1E/D14H5E/D14H1A/D14H5A

9. AUTO CHROMA PHASE The signals that are output from IC1401 are selected by IC2380. Only the sample pulse portion of the selected signal is sampled by IC2381 and is compared with the output by IC2382. The error signal from the comparator is fed back to DAC through IC2383 and automatically controls the PB LEVEL or the R LEVEL until the output agrees with the sampled level. 10. B1 Board The B1 board is an aperture correction circuit. The aperture correction performs the frequency compensation at 5 MHz when the input signal is 480/60i and 575/ 501 with DL400/DL401. It performs the frequency compensation at 16 MHz when any other signals are input. DL404 and DL405 are the delay lines that corrects the delay amount of the Y-signal. The PB and PR signals are corrected of their delay amounts by DL501, DL502, DL503 and DL504. Amount of compensation can be varied by 2 to 6 dB when the APT is ON using the aperture correction amplifier. 11. Sync Separator Circuit/B2 Board The sync separator circuit consists of the sync AGC circuit and the B2 board. Either the input sync signal in the mode of 480/60i and 575/501 or that in any other modes, is selected by IC3301 (2/3), (3/3), Q3302 and Q3303. The sync signal is separated by the SYNC AGC circuit of Q3304 to Q3319. Either INT sync or EXT sync is selected by IC3301. In the B2 board, the equalizing pulses are extracted by IC3901, the H. sync pulse is separated by the H. SYNC SEP. circuit consisting of IC3904, IC3905, IC3906, IC3907 and the V. sync pulse is separated by the V. SYNC SEP. circuit consisting of Q3905, Q3907, Q3908. The switch IC3902 is the selector switch that selects either the internal sync separator output or the already separated H. and V. sync signals that are input when the SDI signal is used.

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