HITACHI C
Instrukcja Serwisowa

R.G.B.
The R.G.B. signals from pins 7,11 and 15 of the scart connector (PL101) are fed to the R.G.B input pins (25,26,27) of IC403. R.G.B operation can be enabled by either taking pin 16 of the scart connector high, this high is fed to Pin 28 of IC403, or via the l²C bus the microprocessor sets IC403 to forced R.G.B mode in which the video processor generates its own fast blank signal. This puts the IC into external R.G.B mode and selects the inputs on pins 25,26 and 27, overriding the video input on pin 20/22. Note: when using R.G.B input the contrast, brightness and colour controls will still operate.

LINE CIRCUIT
Line and frame drive are generated by IC403. The sync pulses are separated from the incoming video signal at pin 18/20/22 and used to control the internal circuitry of the IC. Line drive is produced by counting down the external 4.43MHz crystal at pin 40 to15.625kHz locked to the incoming sync. This drive is output on pin 48 and feeds directly to the line drive transistor Q601. Note: That the output of IC403 Pin 48 is an open-collector and requires a pull up resistor, if the pin is open circuited for test no waveform will be seen. Q601 collector feeds the line output transistor Q603. The line output stage is conventional with a transformer containing a split diode winding for EHT generation. Fifth harmonic tuning is achieved by capacitor C618/619.

FIELD OUTPUT VERTICAL SHIFT
A fly-back pulse is taken from pin 1 of the FBT transformer. This is required by IC403 (Pin 49) for burst / sync gating, and RGB line blanking. The ver_sync signal is output from the pin47 and fed to Pin 41 of IC501. The H_sync pulse is taken from pin 1 of the FBT and fed to the micro at pin 40.These two signals are required by the micro for graphics timing and also for text. IC403 generates a vertical pulse signal VER_OUT and V_AMP that are fed to IC600 (the vertical stage IC). IC600 is supplied by a 26V DC via diode D610.It generates its own ramp signal and based on the V_AMP & VER_OUT signals it produces the vertical deflection signals that are fed to connector PL601. Vertical linearity adjustment is controlled by Q604 which is driven by the PWM output of IC501 at pin 49. Vertical position adjustment is conducted by Q606 derived by the VER_OUT signal. Switching Q606 will change the DC voltage on VOUT_2 pin which will either lower or higher the picture. A DC level is supplied at VOUT_2 via D614 to stabilise the picture and make its position changeable.

B.C.L CIRCUIT (BEAM CURRENT LIMITER)
Beam current limiting is employed to protect the circuitry in the receiver, the CRT and to prevent excessive X Ray radiation in fault conditions. The current drawn by the CRT is monitored by the current drawn through the winding of the fly-back transformer that produces the EHT for the CRT anode. The end of the winding (Pin 10) is returned to IC403 Pins 46, the beam current drawn by the CRT passes through Q603 and develops a voltage on the collector proportional to the current (V=IxR). The voltage on the collector will vary depending on the beam current being drawn reducing the brightness and contrast of the picture. If the voltage is sufficiently negative (indicating very high excess beam current) the output will be reduced, reducing the picture brightness and contrast.

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