AIWA CSDSR540EZK
Instrukcja Serwisowa

Pin No. 43 44 45 46 47 48 49 50 51

Pin Name XVDD XOUT XIN XVSS SBSY EFLG PW SFSY SBCK

I/O � O I � O O O O I Crystal oscillator power supply pin.

Description

Pin to which external 16.9344 MHz crystal oscillator is connected. Crystal oscillator GND pin. Be sure to connect to 0V. Subcode block sync signal output pin. C1, C2, single and dual correction monitoring pin. Subcode P, Q, R, S, T, U and W output pin. Subcode frame sync signal output pin. Falls down when subcode enters standby. Subcode read clock input pin. Schmidt input. (Be sure to connected to 0V when not in use.)

52 53 54 55 56 57 58 59 60 61 62 63 64

FSX WRQ RWC SQOUT COIN
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O O I O I I I O O O I I

Pin outputting the 7.35 kHz sync signal which is generated by dividing frequency of crystal oscillator. Subcode Q output standby output pin. Read/write control input pin. Schmidt input. Subcode Q output pin. Command input pin from microprocessor. Command input read clock or subcode read input clock from SQOUT pin LC78622 reset input pin. Set this pin to L once when the main power is turned on. Test signal output pin. Use this pin as open (normally L output). 16.9344 MHz output pin. 4.2336 MHz output pin. Test signal input pin with built-in pull-down resistor. Be sure to connect to 0V. Chip select signal input pin with built-in pull-down resistor. Be sure to connect to 0V while it is not controlling.

CQCK
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RES TST11 16M 4.2M TEST5
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CS TEST1

I

Test signal input pin without built-in pull-down resistor. Be sure to connect to 0V.

Note: The same potential must be applied to the respective power supply terminals. (VDD, VVDD, LVDD, RVDD, XVDD)

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