jedyne do czego mogę mieć zastrzeżenie to jakość zdjęć zawartych w przesłanej instrukcji serwisowej ponieważ są fatalnej jakości, praktycznie nieczytelne. tak poza tym jestem zadowolony to jest to czego szukałem.
Instrukcja jest OK. Schematy czytelne, opisane niektóre procedury.
Tekstowy podgląd strony 13 (kliknij aby zobaczyć)
Pin No.
Pin Name
1/0 Programmable
Description counter input in the AM band. The PLL command switches between
the direct division method (LF mode) and pulse swallow method (HF mode). With the direct division method, the 0.5-20MHz (0.3Vp-p min.) local oscillation output (VCO output) is input; with thepulse 52 AMIN I oscillation output (VCO output) is input. An input amp is built in, and C-coupling. small-amplitude operation is performed. swallow method, the l-40MHz (0.3 Vp-pmin.) local
Note: If the all the reference internal ports (4 bits) are set to �1�, or FMH mode or FML mode is set, the input is pulled down. Power input. When PLL is operating, 5 V * 10% is applied. The voltage can be dropped to 2 V in the backup status (when the CKSTP command is being executed). If the voltage drops below 3.5 V when the CPU is operating, the CPU will stop to prevent malfunctions. 53 VDD . initialized and the clock corrected by program as required. When the voltage O+ 3.5 V is applied to this pin, the system reset signal will be supplied to the device, and the program will start from address O. Note: Set the rise time of the device supply voltage between 10-100 ms because of the power on reset operation. (See note 1) 54 GND 1 . Ground of the CPU and logic block For the connection of a 7.2MHz crystal oscillator. Adjust the oscillation frequency 55,56 XT, XT (7.2MHz), observing the LCD segment waveforms. The oscillator stops automatically when the CKSTP command is executed. 4-bit (P5- 1- P5-4) I/O port. This port can designate inputs and outputs for every bit: 57-60 P5-1 - P5-4 Ilo the designation is executed by the contents of the internal port called PORT-5 I/O CONTROL. (See notes 1-3) When the voltage rises to more than 3.5 V, the CPU will restart.
This status (Wait mode) can be detected by the Wait F/F bit, so the CPU should be
Note 1: When a reset signal (VDD = O+ 3.5V and INI = �L� + �H�) is input to the device, the I/O ports will be set to inputs, the
common pins of I/O ports and AD/DA converters will be set to inputs of I/O ports, the common pins of I/O ports and serial UO ports will be set to inputs of I/O ports, and the common pins of IF counter inputs and I/O ports will be set to IF counter inputs. Note 2: When the CKSTP command is executed, all outputs of the output ports and I/O ports will be set to �L�. Note 3: When the device is reset, the contents of output ports and internal ports are uncertain, so the device should be initialized by program as required.
