SONY DFP-D3000
Instrukcja Serwisowa

DSP-82 Board
The DSP-82 board performs control over the entire system of the DFP-D3000 and the digital signal processing. The DSP-82 board consists of the following blocks. 1. CPU block 2. External I/O control block 3. DSP block 1. CPU block The main CPU (IC202) is the Intel I960 and OS is pSOS. The CPU block consists of the flash ROM (IC205, IC206), DRAM (IC203, IC204, IC209, IC210), SRAM (IC404, IC450) and the interrupt controller (IC302). The timing adjustment such as arbitration is performed by IC CXD8980 (IC212). When the main power is turned on, all of the OS and the programs stored in the flash ROM are developed in DRAM to be operated on the DRAM. The information such setup data and the preset data that must be stored, are saved in the SRAM which is backed up by battery. The interrupt controller (IC302) handles the ATRAC that is supplied from the DEC-102 board, the ECC interrupt signal and the interrupt signal of the RS-232C communication. 2. External I/O control block RS-232C, AUTOMATION and the signal supplied from other boards are handled as the external I/O signal. RS232C sends and receives signals with external personal computer, and is connected to the CPU bus with a singlechip controller (IC406, Z8532010). The AUTOMATION and the signals supplied from other boards are all controlled by the I/O port (IC405, IC418; CXD1095). CPU performs control by writing and reading data to and from this I/O port with periodic or external interrupt.

3. DSP Block The DSP block consists of the SDDS block and the effect block. . SDDS Block The SDDS data that is supplied from the DEC-102 board, is processed by the SDDS block using DSPs (IC500 to IC503 and IC507 to IC514, TMS57000). The SDDS data consists of three pairs of the P-ch side and the S-ch side respectively (totaling 6 signals). The lip sync delay is added to these signals and the audio timing is adjusted to be in phase with the video signal in this block. The concealment signals are then decoded so that the two systems of the SDDS signal (8 channels) are generated. These signals are selected in accordance with the error status of ECC and receive the digital concealment processing. The signal of the channel in which error occurs, is compensated by the decoded concealment signal. After the digital concealment processing, the signal which has been synchronized with projector, is converted so that is locked to the internal crystal oscillation. When any errors do not occur, the concealment signal processing does not take place and the original 8-channel signal is selected. The selected signal is converted of its clock rate to that generated by the internal crystal. The selected signal is then sent to the effect block. . Effect Block The effect block performs selection of input signal and the various effect signal processing. The effect processing is performed by the DSP SHARC (IC713, IC714; ADSP-61020) manufactured by Analog Devices Inc. In addition to the SDDS signals, the PEC (analog audio output of projector) that has already been A/ D converted by the APR-34 board, AUX signal and other signals are input to DSP. (The input signals such as MIC and NONSYNC are interrupted into the AUX and PEC signals with analog signal level.) DSP selects the desired signal from the various input signals in accordance with the source select status. When the SDDS signal is selected as the source, or when data recovery is not possible even with the digital concealment due to the error status of the SDDS signal, the signal that is assigned to the analog concealment, is selected. The selected input signal receives the various signal processing (matrix, EQ, fader, etc.,) and is output as the 8channel signal to the APR-34 board.

5-2 (E)

5-2 (E)

DFP-D3000