SONY DV-SV97S
Instrukcja Serwisowa

decoding), ADP (audio and JPEG decoding), VPU (sub-picture decoding) and CPU (navigation and DivX DRM). 2.9 VPU - Video Processing Unit The VPU is responsible for all video output processing and timing. It outputs 8 bit (U, Y V, Y interleaved) digital interlaced or progressive SD video with separate syncs and optionally embedded syncs, or digital HD interlaced or progressive video. It can also output interlaced composite, S- or component SD analog video, or progressive components SD analog video The VPU units have three operating modes: SD Interlaced when the digital and analog outputs are interlaced, SD Progressive when the digital output is progressive. In this mode, the analog output can be either SD interlaced or progressive. A two fields Deinterlacer can be used (as needed) for the decoded image. The third mode is HD interlaced or progressive digital output with no analog output. In this mode, all VPU units apart from the HDI and Sync Generator and Sync Receiver are not operating. The VPU has a sync generator and output unit. The sync signals are used by the sync receiver unit to generate all video timing for all other VPU units and timing signals for the CPU and PDU. The image post-processing unit can scale the stored image (horizontally and vertically with scale ratios of 1/2 to 16) and shift it with ¼ pixel resolution. Then, it can enhance the image and pad it with background colour. In addition, the VPU has a DVD sub-picture decoding unit. The sub-picture is blended with the enhanced image. The resulting image is blended with an OSD image generated by a 2, 4 or 8 bits per pixel OSD Decoder. Finally, closed captions is added to generate the final digital video. The final interlaced digital video is processed by the video encoder to generate six 10 bit video streams. One stream is composite video, the next two are the luma and composite chroma components of the S-Video format. The three other streams are color components, either Y,U,V or R,G,B. Four of the six streams are converted to analog by four on-chip 54 MHz DACs. For three of the four DACs, the selected combination can be: (a) Interlaced composite and S-Video; (b) Three interlaced components (either Y,U,V or R,G,B); (c) Three progressive Y,U,V components. For cases (a) and (b), the fourth DAC can output either the composite signal, the luma (Y) signal, or the chroma (C) signal of the S-Video. The final progressive digital video is processed by the video encoder to generate three 10 bit video color components streams, either Y,U,V or R,G,B. The streams are converted to analog by three on-chip 54 MHz DACs. The fourth DAC has no output. 2.10 ADP - Audio Data Processor The ADP is the audio processing unit of the Vaddis 778. It is based on a 32 bits data and 32 bits instruction ADP76 core. The ADP core has attached to it 24 KWords (32 bits) instruction ROM, 2 banks of 8 KWords (32 bits) each of data ROM, 6 KWords (32 bits) instruction RAM, 8 KWords (32 bits) data RAM, 1 KWords (32 bits) data DMA caches, and several peripheral units mentioned below, including units to assist JPEG decoding. The peripherals are DMA interface unit, audio code interface unit, CPU and DVP interface unit, real-time clock unit, serial port unit (including a S/PDIF input receiver) and interrupt handler. The JPEG assist units are VLC Decoder and interface to the PRU that will execute dequantization and IDCT. All the ADP peripheral units are connected to the ADP core through the AP_Bus (audio peripherals bus). The interrupt handler is also connected directly to the interrupt port of the ADP core.