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...instruction is ok.
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Documentation made available quickly and It is good quality. Thanks.
Pin No.
60 61 62 63 64 65 66 67 68 69 70 71 72~79 80 81 82 83 84 85 86,87 88 89 90 91 92~99 100
Pin Name
VSS RAMA4 /IC TEST RAMA3 /CSB /CS SO SI SCK RAMA2 VDD1 RAMD0~7 VSS VDD2 SDWCK0 SDBCK0 SDIA0 SDIA1 RAMA1,0 RAMWEN RAMOEN VSS VDD2 IPORT7~0 VSS
I/O
O I O I I O I I O I/O (Not used) I I I I O O O I Ground. Ground.
Description
External SRAM Interface address 4. (Not used) Initial clear. Test terminal (Not used). External SRAM Interface address 3. (Not used) Sub DSP Chip select. Microprocessor interface Chip select. Microprocessor interface Serial data output. Microprocessor interface / Sub DSP Serial data input. Microprocessor interface / Sub DSP clock input. External SRAM Interface address 2. (Not used) +5V power supply (for I/Os). External SRAM Interface data (STREAM0~7 output when External SRAM is not in use).
+3.3V power supply (for core logic). Word clock input for SDIA, SDOA, SDIB, SDOB. Bit clock input for SDIA, SDOA, SDIB, SDOB. AC-3 bitstream (or PCM ) data input for Main DSP. AC-3 bitstream (or PCM ) data input for Main DSP. External SRAM Interface address 1, 0. (Not used) External SRAM Interface / WE. (Not used) External SRAM Interface / OE. (Not used) Ground. +3.3V power supply (for core logic). Input port for general purpose. Ground.
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