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Dla tego produktu nie napisano jeszcze recenzji!
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Dokładna dokumentacja, pomogła w szybkiej naprawie telewizora. Dziękuję!
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jedyne do czego mogę mieć zastrzeżenie to jakość zdjęć zawartych w przesłanej instrukcji serwisowej ponieważ są fatalnej jakości, praktycznie nieczytelne. tak poza tym jestem zadowolony to jest to czego szukałem.
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Wszystko w porządku.
Instrukcja czytelna i kompletna.
Dziękuję.
all right!
thank you.
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Bardzo dobra instrukcja. Zawiera wszystko co potrzeba, polecam!
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Instrukcja jest OK. Schematy czytelne, opisane niektóre procedury.
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[3] Downloading Sequence
A
� Downloading the firmware to the AUDIO DSP
Downloading the firmware to the AUDIO DSP is performed in 4 sessions. 1. After reset of the AUDIO DSP is canceled, DSPCS# is set to �L.� Then transfer of the initialization program 1 starts. 2. After the transfer is completed, it is checked that DSPCS# is set to �H.� Then DSPDREQB# is set to �L.� 3. DSPCS# is set to �L.� Then transfer of the initialization program 2 starts. 4. After the transfer is completed, it is checked that DSPCS# is set to �H.� Then DSPDREQB# is set to �H.� 5. DSPCS# is set to �L� then transfer of the initial values starts. 6. After the transfer is completed, it is checked that DSPCS# is set to �H.� Then DSPDREQB# is set to �L.� 7. DSPCS# is set to �L.� Then transfer of the program for the main unit starts. 8. After the transfer is completed, it is checked that DSPCS# is set to �H.� Then DSPDREQB# is set to �H.� Downloading is completed. DSPCS# (Pin 50)
B
SPICLK (Pin 53) SPIOUT (Pin 55) DSPDREQB# (Pin 27) Approx. 110 msec Note: The above-mentioned pin numbers are those of the IC202 (SOUTH CPU). Transfer of the initialization program 1 Transfer of the initialization program 2 Transfer of the initial values Transfer of the program for the main unit
C
� Downloading the firmware to the FPGA
1. The FPGRM is set to �H.� 2. It is checked that SD2_OUT is set to �H.� 3. Transfer of the FPGA firmware starts. 4. After the transfer is completed, it is checked that DONE is set to �H.� 5. After a wait of 1 ms or more, FPGARST# is set to �H� (released). Downloading is completed. FPRGM (Pin 38) SD2_OUT (Pin 36) SPICLK (Pin 53)
D
SPIOUT (Pin 55) FDONE (Pin 37) FPGARST# (Pin 46)
Transfer of the FPGA firmware 1 ms or more
Approx. 200 msec Note: The above-mentioned pin numbers are those of the IC202 (SOUTH CPU).
E
F
52
1 2
MEP-7000
3 4
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