jedyne do czego mogę mieć zastrzeżenie to jakość zdjęć zawartych w przesłanej instrukcji serwisowej ponieważ są fatalnej jakości, praktycznie nieczytelne. tak poza tym jestem zadowolony to jest to czego szukałem.
NAME I/O FUNCTION VDD1 - +5V power supply (for I/Os) RAMCEN O External SRAM Interface /CE RAMA16 O External SRAM Interface address 16 RAMA15 O External SRAM Interface address 15 SDIB0 I+ PCM input 0 to Sub DSP SDIB1 I+ PCM input 1 to Sub DSP SDIB2 I+ PCM input 2 to Sub DSP XI I Crystal oscillator connection or input external clock (12.288 MHz) XO o Crystal oscillator connection VSS - Ground AVDD - +3.3V power supply (for PLL circuit) SDIB3 I+ PCM input 3 to Sub DSP TEST Test terminal (to be open in normal use) TEST Test terminal (to be open in normal use) OVFB O Detection of overflow at Sub DSP DTSDATA O DTS data detection (Refer to "Status Register".) AC3DATA O AC-3 data detection (Refer to "Status Register" .) SDOB3 O PCM output from Sub DSP CPO A Output terminal for PLL, to be connected to ground through the external analog filter circuit. (Refer to "External Circuit for PLL" .) AVSS - Ground (for PLL circuit) VDD2 - +3.3V power supply (for core logic) SDOA2 o PCM output from Main DSP (C, LFE) SDOA1 O PCM output from Main DSP (LS, RS) SDOA0 O PCM output from Main DSP (L, R) RAMA14 O External SRAM Interface address 14 RAMA13 O External SRAM Interface address 13 RAMA12 O External SRAM Interface address 12 RAMA11 O External SRAM Interface address 11 RAMA10 O External SRAM Interface address 10 VSS - Ground VDD1 - +5V power supply (for I/Os) OPORT0 O Output port for general purpose. (Refer to " OPORT Register") OPORT1 O Output port for general purpose. (Refer to " OPORT Register") OPORT2 O Output port for general purpose. (Refer to " OPORT Register") OPORT3 O Output port for general purpose. (Refer to " OPORT Register") OPORT4 O Output port for general purpose. (Refer to " OPORT Register") OPORT5 O Output port for general purpose. (Refer to " OPORT Register") OPORT6 O Output port for general purpose. (Refer to " OPORT Register") OPORT7 O Output port for general purpose. (Refer to " OPORT Register") VSS - Ground VDD2 - +3.3V power supply (for core logic) RAMA9 O External SRAM interface address 9 RAMA8 O External SRAM interface address 8 RAMA7 O External SRAM interface address 7 SDOB2 O PCM output from Sub DSP SDOB1 O PCM output from Sub DSP SDOB0 O PCM output from Sub DSP SDBCK1 I+ Bit clock input for SDOA, SDIB, SDOB. (Refer to " SDOA, SDIB, SDOB Register") SDWCK1 I+ Word clock input for SDOA, SDIB, SDOB. (Refer to " SDOA, SDIB, SDOB Register") VSS - Ground
CRC (30MHz) Data RAM AC3DATA ERAMUSE Delay RAM DTSDATA PLL
I/O O O O O O O O O O Is O Is+ Is Ot Is Is O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I+/O I I I I O O O O I+ I+ I+ I+ I+ I+ I+ I+
FUNCTION +3.3V power supply (for core logic) Detection of non PCM data. (Refer to " Status Register") Detection of AC-3 CRC error. (Refer to " Status Register") Detection of auto-mute. (Refer to " Status Register") Detection of AC-3 karaoke data. (Refer to " Status Register") Detection of AC-3 2/0 mode Dolby surround encoded input (Refer to " Status Register") Inverted SDBCKO clock output (refer to " Block diagram") External SRAM Interface address 6 External SRAM Interface address 5 Ground External SRAM Interface address 4 Initial clear Test terminal (to be open in normal use) External SRAM Interface address 3 Sub DSP Chip select Microprocessor interface Chip select Microprocessor interface Serial data output Microprocessor interface/Sub DSP Serial data input Microprocessor interface/Sub DSP clock input External SRAM Interface address 2 +5V power supply (for I/Os) External SRAM Interface data (STREAM 0 output when External SRAM is not in use) External SRAM Interface data (STREAM 1 output when External SRAM is not in use) External SRAM Interface data (STREAM 2 output when External SRAM is not in use) External SRAM Interface data (STREAM 3 output when External SRAM is not in use) External SRAM Interface data (STREAM 4 output when External SRAM is not in use) External SRAM Interface data (STREAM 5 output when External SRAM is not in use) External SRAM Interface data (STREAM 6 output when External SRAM is not in use) External SRAM Interface data (STREAM 7 output when External SRAM is not in use) Ground +3.3V power supply (for core logic) Word clock input for SDIA, SDOA, SDIB, SDOB (Refer to " SDIA, SDOA, SDIB, SDOB Register") Bit clock input for SDIA SDOA SDIB SDOB (Refer to " SDIA, SDOA, SDIB, SDOB Register") AC-3/DTS bitstream (or PCM) data input for Main DSP (Refer to " SDIA Register") AC-3/DTS bitstream (or PCM) data input for Main DSP (Refer to " SDIA Register") External SRAM Interface address 1 External SRAM Interface address 0 External SRAM Interface /WE External SRAM Interface /OE Ground +3.3V power supply (for core logic) Input port for general purpose (Refer to " IPORT Register") Input port for general purpose (Refer to " IPORT Register") Input port for general purpose (Refer to " IPORT Register") Input port for general purpose (Refer to " IPORT Register") Input port for general purpose (Refer to " IPORT Register") Input port for general purpose (Refer to " IPORT Register") Input port for general purpose (Refer to " IPORT Register") Input port for general purpose (Refer to " IPORT Register") Ground Schmidt trigger input terminal Input terminal with a pull-up resistor Digital output terminal Tri-state digital output terminal Analog terminal
