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Kto jest w sklepie?
Sklep przegląda 6043 gości
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Dla tego produktu nie napisano jeszcze recenzji!
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Schematy są ale można wysilić się i zrobić kolorowy skan i o większej rozdzielczości. Wtedy schematy płytek będą czytelniejsze. Całość super jako wartość merytoryczna. Wszystkie dane potrzebne do podłączenia różnego rodzajów urządzeń takich gramofon, CD itd.
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Szybko, sprawnie i tanio. Serwis godny polecenia. Będę polecał innym
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Ogólnie jest OK, z wyjątkiem obrazu płyty głównej, który jest miejscami mało czytelny, ale można sobie poradzić.
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Dokładna dokumentacja, pomogła w szybkiej naprawie telewizora. Dziękuję!
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jedyne do czego mogę mieć zastrzeżenie to jakość zdjęć zawartych w przesłanej instrukcji serwisowej ponieważ są fatalnej jakości, praktycznie nieczytelne. tak poza tym jestem zadowolony to jest to czego szukałem.
It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7118E accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-PB -PR or RGB. An expansion port (X-port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7118E supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers. The target application for the SAA7118E is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing. 12.23.2. Features Video acquisition/clock � Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. Vestigial Side Band (VSB) signals) � Up to eight analog Y + C inputs, split as desired � Up to four analog component inputs, with embedded or separate sync, split as desired � Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs) � Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals � Switchable white peak control � Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz) � Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties � On-chip line-locked clock generation in accordance with �ITU 601� � Requires only one crystal (32.11 or 24.576 MHz) for all standards � Horizontal and vertical sync detection. Video decoder � Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR � Automatic detection of any supported colour standard � Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM � Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals � Increased luminance and chrominance bandwidth for all PAL and NTSC standards � Reduced cross colour and cross luminance artefacts � PAL delay line for correcting PAL phase errors � Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals � User programmable sharpness control � Detection of copy-protected signals according to the macrovision standard, indicating level of protection � Independent gain and offset adjustment for raw data path. Component video processing � RGB component inputs � Y-PB -PR component inputs � Fast blanking between CVBS and synchronous component inputs � Digital RGB to Y-CB -CR matrix. Video scaler � Horizontal and vertical downscaling and upscaling to randomly sized windows � Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: H and V zoom are restricted by the transfer data rates) � Anti-alias and accumulating filter for horizontal scaling � Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy) � Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width) 27 Plasma TV Service Manual 24/10/2003
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