CASIO SF-8500
Instrukcja Serwisowa

8)

Gate array

GND

When VDD is applied from power supply IC SC371015FU to gate array µPD65005GC-556Open (Pin 26) (Pin 25) MON

3B6, gate array will send "L" signal to active the main switch signal from terminal SWO. Also, gate array will send "H" signal to release the INT0 terminal of CPU from LSO terminal. The terminal CSB is for the chip select of gate array. This signal is sent from CPU terminal CS2. And when the VDD is applied to CPU, CPU will send "H" signal to CSB terminal.

"L"

TO MAIN SWITCH (Pin 40) SWO

LSI GATE ARRAY

µPD65005GC-566-3B6
"H" TO CPU INT0 terminal (Pin 70) (Pin 27) LSO (Pin 7) (Pin 33)

(Pin 34)

VDD

GND

CSB (Pin 24) "H" FROM CPU CS2 terminal (Pin 28)

9)

Main switch and power on switch
VDD

MAIN SWITCH (Pin36) SW "L" OFF ON (Pin40) "L"

GATE ARRAY
SWO

CPU
HD62076C02

µPD65005GC-566-3B6

KAC (Pin54) "L"

KIO (Pin53) "H"

POWER ON SWITCH

When the main switch is set to on position, SW terminal of CPU becomes "L", then CPU will send "L" signal to KAC terminal to enable the system power on. The KI0 terminal is "H" when VDD is applied to CPU. Therefore, when pressing the power on switch, CPU will generate a clock pulse (2 MHz) for start up the system.

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