SONY YS-W170
Instrukcja Serwisowa

R6 and R7 are a base current limiting resistor (Q1). This resistor limits the current supplied to the base of Q1. R5 and R26 are an overcurrent detection resistor. This resistor monitors the voltage generated in R5 and R6 using a collector current that flows through Q1, controlling the oscillating frequency of Q1 by Q2. * In an RCC switching system, Q1 enters the ON state when a voltage is applied from the full-wave rectified voltage to the base through starting resistors R2 and R3. Next, a current flows through the No. 1 to No. 3 windings (main winding on the primary winding) of T1, and a voltage is also generated in No. 5 and No. 6 windings (auxiliary winding on the primary winding). The voltage generated in No. 5 and No. 6 windings (auxiliary winding on the primary winding) is regulated by Q3, D4, D5, R8, and R9 and then applied to the base of Q1. Moreover, the voltage accelerates the ON state. The base current supplied from the No. 5 and No. 6 windings is limited by R6 and R7. The collector current of Q1 is put into the saturation state. The voltage of No. 5 and No. 6 windings (auxiliary winding on the primary winding) decreases as the voltage between the collector and emitter increases. Q1 then rapidly transits to the OFF state. At that time, the energy stored on each secondary winding of T1 is output via D8, D9, and D10. The primary winding is reset when the energy stored on the secondary winding is lost. Q1 is turned on again. An ON duty-variable oscillating frequency is controlled while this cycle is repeated. The voltage induced to the No. 11 and No. 12 windings of T1 is rectified by D8 and then smoothed by C11 to produce a voltage of +12 V. A voltage of +9 V is produced from the +12 V voltage by IC1 (three-terminal regulator). The voltage induced to the No. 9 and No. 10 windings of T1 is rectified by D9 and then smoothed by C16 to produce a voltage of +8 V. A voltage of +5 V is produced from the +8 V voltage by IC2 (three-terminal regulator). The voltage induced to the No. 8 and No. 7 windings of T1 is rectified by D10 and then smoothed by C21 to produce a voltage of +31 V. When a voltage of +31 V increases abnormally, the upper limit is clamp-controlled to 39 V by D11. R10 and R11 are a dummy resistor used to suppress the increase in a voltage during non-load (when a camera is not connected). The dummy resistor monitors an output voltage of +31 V to improve the precision of an output voltage and feeds the cathode current of IC3 (shunt regulator) back to the primary winding via PH1. 3-2

5. Sync block During PRIMARY setting The output signal of IC104 is set �high�, the 14.31818 MHz (CE: 14.18750 MHz) signal from a crystal oscillator circuit is input to IC107, and a VS/VD signal is output. The VS signal is divided in resistance and sent to IC120 (2/3). The VD signal is passed through a shift register (IC109) to determine the pulse width using a monostable multivibrator (IC110) and sent to IC120 (2/3). A �high� or �low� signal is output according to the setting of a PRIMARY/SECONDARY selector switch. Moreover, the control terminal of IC120 (3/3) is controlled and a superimposed sync signal is generated. A SYNC OUT signal is output from IC120 (1/3) under the same control. During SECONDARY setting The external sync signal input from the SYNC IN terminal is cut in a DC level for sync separation by IC151. A VS signal is output from IC112 and branched to two paths. One is sent through a buffer (Q119) to IC117 (1/3). The other is sent to a sync discriminator circuit (IC119). A VD signal is output from IC116 and branched to two paths. One is sent through a buffer (Q120) to IC117 (2/3). The other is sent to a sync discriminator circuit (IC122). If each input signal of a sync discriminator circuit is normal, the output signal is set �high�. The output signal is input to the gate of AND circuit IC123. The resultant output signal is input to the control terminal of multiplexer IC117 (1/3 and 2/3) to discriminate whether the signal input from the SYNC IN terminal is a VD or VS signal. Moreover, a �high� or �low� signal is output according to the setting of the VD/VS selector switch on the front panel. In this case, the control terminal of IC117 (3/3) is controlled and the VD/VS setting is confirmed. During PRIMARY setting, the same confirmation as above is done by IC120 (2/3). No superimposed sync signal is output if the input signal from the SYNC IN terminal differs from the switch setting on the front panel. A �high� or �low� signal is output according to the setting of a PRIMARY/ SECONDARY selector switch. Moreover, the control terminal of IC120 (3/3) is controlled and a superimposed sync signal is generated. A SYNC OUT signal is output from IC120 (1/3) under the same control.

3-5. SW-1072 Board
User control switches and LEDs are mounted on the SW1072 board.

YS-W170/W170P (E)